This disclosure relates generally to the field of semiconductor manufacturing, and more particularly to forming a field effect transistor (FET) device with a stressed channel region.
Mechanical stresses within a semiconductor device substrate may be used to modulate device performance. For example, in silicon (Si) technology, the channel of a FET may be oriented along the {110} planes of silicon. In this arrangement, hole mobility is enhanced when the channel is under compressive stress in the film direction and/or under tensile stress in a direction normal of the channel, while the electron mobility is enhanced when the silicon film is under tensile stress in a direction normal of the channel. Therefore, compressive and/or tensile stresses can be advantageously created in the channel regions of a p-type FET (PFET) or an n-type FET (NFET) in order to enhance the performance of such devices.
One possible approach for creating a desirable stressed channel region is to form embedded silicon germanium (SiGe) for PFET or silicon carbide (SiC) for NFET source/drain stressor material in stress cavities in the source/drain regions of a FET device to induce compressive or tensile strain in the channel region which is located between the source and drain regions. The source/drain stressor material may be heavily doped in situ to avoid implant damage to the stressor that can degrade the channel stress. While the channel stress increases as the stressor proximity to the channel decreases, close proximity of the highly doped source/drain stressor material to the FET channel may degrade the electrostatics of the finished stressed channel FET device. Particularly, heavily doped source/drain material in close proximity to the channel region may exacerbate short channel effect and punchthrough issues, and may also increase parasitic leakage, junction capacitance, and floating body effects from band to band tunneling during FET operation.